Digital-to-analog converter and method for reducing harmonic distortion in a digital-to-analog converter

ABSTRACT

The invention relates to a digital-to-analog converter. In order to reduce distortion in the output, the converter comprises a first and a second current output (OUT, XOUT), at least two current sources ( 1 ) and assigned to each of the current sources ( 1 ) a current switch circuit. Each current switch circuit comprises means ( 4, 5, 6, 7 ) for creating two overlapping complementary control signals out of a signal indicating whether the current source ( 1 ) is selected, while in a first group of the current switch circuits the connection of the current source ( 1 ) to the current outputs is controlled by one of the control signals respectively, and while in a second group of the current switch circuits the control by the control signals is exchanged, each of the current switch circuits of the second group comprising in addition means ( 10 ) for inverting the signal input to the means for creating two overlapping complementary control signal ( 4, 5, 6, 7 ).

PRIORITY CLAIM

This is a national stage of PCT application No. PCT/EP01/03234, filed onMar. 21, 2001. Priority is claimed on that application.

FIELD OF THE INVENTION

The invention relates to a digital-to-analog converter and to a methodfor reducing harmonic distortion in a digital-to-analog converter.

BACKGROUND OF THE INVENTION

Digital-to-analog (D/A) converters are used in a variety of applicationsfor converting digital signals into corresponding analog signals. Theyare employed for example in base stations and in radio relaytransmitters. The purity of the analog output signal is often of greatsignificance for the performance of the application.

In current-steering D/A converters, the analog output signal is formedby connecting a number of current sources to a current output. In mostof the applications, each current source is steered to one of twocurrent outputs, resulting in a differential output signal current.

FIG. 1 shows as an example a segmented current steering 10-bit D/Aconverter with a 6-bit MSB (most significant bits) block formed of 63unweighted current sources 1 and a 4-bit LSB (least significant bits)block formed of four binary-weighted current sources. To each currentsource there is assigned a differential switch pair S controlled by acurrent switch circuit and used to steer the respective current sourceto one of two current outputs OUT and XOUT. The four current sources ofthe LSB block output a one-, two-, four- and eight-fold predeterminedcurrent respectively if selected, thereby enabling an output of 8different current values. Each of the current sources of the MSB blockoutputs a 16-fold predetermined current if selected. Each current sourceof the MSB block is responsible for a stepwise increase of the outputcurrent signal by a 16-fold predetermined current 16I when selected,thereby enabling an output of 64 different current values. The currentsof the MSB and the LSB blocks are summed to form the output signal.

Today it is possible to design an integrated current steering D/Aconverter for sampling frequencies of up to several hundreds ofmegasamples per second with a resolution of up to 14 bit. However, withresolutions of 10 bit or more, the full resolution bandwidth is limitedto several megahertz. In telecommunications applications a signalbandwidth of several megahertz is required.

The limiting factor for an effective resolution with high frequencysignals is distortion. Timing errors and code dependency of the outputimpedance contribute to distortion. The most common cause of distortion,however, is asymmetrical glitches that occur during the state changes inthe differential switches. If the resolution of a D/A converter is equalto or more than 10 bit, distortion starts to limit the dynamic linearityrapidly after some critical point of usually less than 10 MHz.

For illustration, FIG. 2 shows a simulated spectrum of the D/A converterof FIG. 1, the output voltage V_(out) being depicted over the frequencyf/Hz of the outputted signal. The used sampling rate is 200 MHz and thesignal frequency 20 MHz. Even though the output signal is differential,the even order harmonic components are high. The 2^(nd) order harmoniclimits the SFDR (spurious free dynamic range) to 53 dB. This illustratesthat the differential output is not symmetrical in practice.

Attempts to improve the spectrum are known from the state of the art.Most published methods focus on decreasing the glitch energy in order toimprove the spectral purity, but the 2^(nd) harmonic component can stillappear in the spectrum. Moreover, the 2^(nd) harmonic usually dominatesthe distortion. Such methods are described for example in Analog DevicesAD9754 Datasheet: “14-bit, 125MSPS High Performance TxDAC D/AConverter”, Analog Devices, Inc., 1999; J. Bastos, A. M. Marques, M. S.J. Steyaert, W. Sansen: “A 12-bit Intrinsic Accuracy High-Speed CMOSDAC”, IEEE J. Solid-State Circuits, vol. 33, no. 12, December 1998, pp.1959-1969; J. Vandenbussche, G. Van der Plas, A. Van den Bosch, W.Daems, G. Gielen, M. Steyaert, W. Sansen: “A 14-bit 150 MSamples/sUpdate Rate Q² Random walk CMOS DAC”, Proc. IEEE Int. Solid-StateCircuits Conf., February 1999, pp. 146-147; and A. Van den Bosch, M.Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J. Bastos, M.Steyaert, G. Gielen, W. Sansen: “A 12-bit 200 MHz Low Glitch CMOS D/AConverter”, Proc. Custom Integrated Circuits Conference, 1998, pp.249-252.

Another proposed possibility is to use track-and-hold circuitry in theoutput, as disclosed in A. R. Bugeja, B. -S. Song, P. L. Rakers, S. F.Gilling: “A 14-bit 100 MSamples/s CMOS DAC Designed for SpectralPerformance”, Proc. IEEE Int. Solid-State Circuits Conference, February1999, pp. 148-149 and A. Bugeja, B. -S. Song: “A Self-Trimming 14 b 100MSample/s CMOS DAC”, Proc. IEEE Solid-State Circuits Conference,February 2000, pp. 44-45. The settled signal from the output is trackedso that the state change phase cannot be seen in the output signal. Theusage of a track-and-hold circuit in the output increases the complexityof the D/A converter and the current consumption and is not verypractical in mobile terminal units. In addition the speed of the systemis limited by the sampling circuitry.

Finally, a few published solutions, like U.S. Pat. No. 6,031,477 and D.A. Mercer, L. Singer: “12-bit 125MSPS CMOS D/A Designed For SpectralPerformance”, International Symposium on Low Power Electronics andDesign, 1996, pp. 243-246, focus on improving the timing accuracy in thesingle current switch circuits. With these methods, however, thereremains some finite signal frequency dependent distortion.

SUMMARY OF THE INVENTION

It is an object of the invention to reduce distortion in the output of asegmented current steering D/A converter.

The object is reached on the one hand by a digital-to-analog convertercomprising a first and a second current output, at least two currentsources, the currents of the current sources being summed to form ananalog output signal, and assigned to each of the current sources acurrent switch circuit for connecting the respective current source tothe first current output if the current source is selected according toa digital input signal and for connecting the respective current sourceto the second current output if the current source is not selectedaccording to the digital input signal, each current switch circuitcomprising means for creating two overlapping complementary controlsignals out of a signal indicating whether the current source isselected, while in a first group of the current switch circuits theconnection of the respective current source to the first current outputis controlled by the first one of the overlapping control signals andthe connection of the current source to the second current output iscontrolled by the second one of the overlapping control signals, andwhile in a second group of the current switch circuits the connection ofthe respective current source to the first current output is controlledby the second one of the overlapping control signals and the connectionof the current source to the second current output is controlled by thefirst one of the overlapping control signals, each of the current switchcircuits of the second group comprising in addition means for invertingthe signal input to the means for creating two overlapping complementarycontrol signals.

On the other hand, the object is reached by a method for reducingharmonic distortion in a digital-to-analog converter comprising a firstand a second current output, at least two current sources, the currentsof the current sources being summed up to form an analog output signal,and assigned to each of the current sources a current switch circuit forconnecting the respective current source to the first current output ifthe current source is selected according to a digital input signal andfor connecting the respective current source to the second currentoutput if the current source is not selected according to the digitalinput signal, the method comprising

creating for each current source of a first group of current sources twooverlapping control signals based on a signal indicating whether therespective current source is selected, and using the first of saidoverlapping control signals for controlling the connection of thecurrent source to the first current output and the second of saidoverlapping control signals for controlling the connection of thecurrent source to the second current output; and

creating for each current source of a second group of current sourcestwo overlapping control signals based on a signal which is invertedcompared to the signal indicating whether the respective current sourceis selected, and using the first of said overlapping control signals forcontrolling the connection of the current source to the second currentoutput and the second of said control signals for controlling theconnection of the current source to the first current output.

According to the invention, a certain number of current switch circuitsassigned to the current sources of a D/A converter is divided into twogroups. The first group switches the respective current source to afirst or a second current output conventionally. To this end, thecurrent switch circuits create overlapping control signals out of aninformation indicating whether the current source is presently selected.The current switch circuits of the second group, however, are modified.The connection of the outputs of the means for creating overlappingsignals to the actual switching means is switched. Additionally, thesignal entering the means for creating overlapping signals is inverted.As a result, the connections between the current source and the firstand the second current output are controlled with signals of the samestate as if a current switching circuit of the first group wereemployed, when disregarding the overlaps. The asymmetry of the overlaps,however, is changed.

Since part of the state changes now occur in a complementary way ascompared to the other part of the state changes, the asymmetricalglitches occurring during the state changes in the switches arecompensated in the summed up analog output signal. This means that thedistortion caused by the pulse relation errors in the control signalsspreads to the noise floor or at least decreases significantly.

It is an advantage of the invention that is does not necessitate anincrease in the current consumption. Nor is the circuit complexityincreased, since only an inverter has to be added to realize themodified current switch cells. Another significant advantage is given bythe fact that there is no signal frequency dependency of thecompensation according to the invention.

Preferred embodiments of the invention become apparent from thesubclaims.

Many D/A converters comprise weighted, in particular binary-weighted,current sources for converting the least significant bits (LSB) of adigital signal and unweighted current sources for converting the mostsignificant bits (MSB) of a digital signal. In such a converter it ispreferred that only the current switch circuits assigned to theunweighted current sources are divided into two groups for acomplementary controlling of the connection of the current sources to afirst and a second current output. The weighted current sources arecontrolled conventionally, because they have different impacts on theresulting asymmetry.

Preferably, the two groups of current switch circuits are basically ofequal size in order to achieve an optimal compensation.

In an advantageous embodiment of the invention, two parallel arrays ofcurrent sources are employed. These two arrays are used simultaneously,i.e. with each change of state (at least) one current source of eacharray is switched at the same time. The current switch circuits assignedto the current sources of the first array all belong to the first group,the current switch circuits assigned to the current sources of thesecond array all belong to the second group of current switch circuits.Accordingly, in every switch transition both a modified and anunmodified cell switches at the same time. This leads to an even bettercompensation of the asymmetries, since the compensation takes placeimmediately and exactly matched with each switch and since an unevendistribution of carried out switches is irrelevant in thisimplementation. Moreover, this embodiment of the invention is alsosuitable for including the weighted current sources in the compensation,since the asymmetries caused by the switching of a current source in thefirst array are always compensated by the switching of an equal currentsource of the second array.

The digital-to-analog converter and the method according to theinvention are especially suited to be used in base stations and radiorelay transmitters.

BRIEF DESCRIPTION OF THE FIGURES

In the following, the invention is explained in more detail withreference to drawings, of which

FIG. 1 shows the general structure of a segmented current steering D/Aconverter;

FIG. 2 shows the simulated spectrum of an output signal of a 10-bit D/Aconverter without compensation;

FIG. 3a shows a known current switch employed in an embodiment of theinvention;

FIG. 3b shows a modified current switch employed in an embodiment of theinvention;

FIG. 4 shows the switching order of a 6-bit block of current sources inan embodiment of the invention;

FIG. 5 shows a simulated spectrum of an output signal of a 10-bit D/Aconverter with compensation according to the invention;

FIG. 6 shows a simulated spectrum of an output signal of a 13-bit D/Aconverter without compensation; and

FIG. 7 shows a simulated spectrum of a 13-bit D/A converter withcompensation according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

The segmented current steering D/A converter of FIG. 1 and the spectrumof the output signal of FIG. 2 have already been described above. The10-bit D/A converter of FIG. 1 is also the basis for the describedembodiment of the invention.

FIGS. 3a and 3 b schematically show a first and a second current switchcell in a current steering D/A converter of FIG. 1. In both cells, acurrent switch circuit is used for the steering of one of the currentsources 1 of the MSB-block of FIG. 1 by controlling a differentialswitch pair S.

Each of the current sources 1 of the MSB block of FIG. 1 is destined tooutput a differential current depending on the 6-bit MSB part in adigital signal that is to be converted into an analog signal. Oneexample of determining the switching order of the current sources 1 canbe taken from FIG. 4, in which each of the 63 current sources is definedas a cell in a matrix by a pair of a column 1-8 and a row 1-8. Each ofthe current sources 1 belonging to columns 8, 6, 4 and 2 in FIG. 4 isconnected by a first current switch circuit according to FIG. 3a to oneof the current outputs OUT, XOUT. Each of the current sources 1belonging to one of columns 1, 3, 5 and 7 in FIG. 4 is connected by asecond current switch circuit according to FIG. 3b to one of the currentoutputs OUT, XOUT. The cells corresponding to the latter current sources1 are marked with an X in FIG. 4. The 6-bit MSB signals can be decodedinto 64 decoded signals. These 64 signals can then control all 63switching cells.

In FIG. 3a, an input line providing an input signal IN is connected theinput of a D-flipflop 2 which receives additionally at its timing inputa clock signal CLK. The two complementary output signals of theD-flipflop Q and QZ are input to a latch circuit 3 the output lines ofwhich are both connected to a respective inverter 4, 5. The output ofeach of the inverters 4, 5, finally, is coupled to the base of one oftwo transistors 6, 7 forming a differential switch pair S. Thetransistors 6, 7 are suitable to connect a current source 1 to one oftwo different current outputs OUT and XOUT respectively.

The current switch circuit of FIG. 3a is used for steering half of thecurrent sources 1 of the MSB block of FIG. 1 and works as follows:

The input signal IN indicates in accordance with the 6 bit MSB part ofthe present 10-bit digital signal whether a current source has to beselected to provide a current. If the current source is to be selected,a high input signal IN is input to the D-flipflop 2, otherwise a lowinput signal IN. The D-flipflop 2 synchronizes the signal IN with therising edge of the clock signal CLK and outputs the synchronized signalQ and a complementary synchronized signal QZ. The synchronized signal Qand complementary synchronized signal QZ are fed to the latch circuit 3and the inverters 4, 5 which are used to generate overlapping controlsignals for the transistors 6, 7 of the differential switch pair S.

The differential switch pair S connects the current source 1 to one ofthe current outputs OUT and XOUT according to the overlapping controlsignals. Since the control signals are overlapping, the connection ofthe current source 1 to one or the other of the current outputs OUT,XOUT is overlapping as well, i.e. for a short period of time after eachswitch, the current source 1 is connected to both current outputs OUT,XOUT in parallel. This way a period of time without connection to one ofthe current outputs OUT, XOUT because of timing delays in one of thecontrol signals is prevented. That means that the switching waveformsare overlapping in order to prevent the current source to drop out ofits saturation region. The overlaps are different for the two switchingdirection OUT to XOUT and XOUT to OUT which leads to the harmonicdistortions described with reference to the state of the art anddepicted in the simulated spectrum of FIG. 2, if the current switchcircuit of FIG. 3a is employed for all current sources 1 of the D/Aconverter.

The current switch circuit of FIG. 3b comprises the same elements 2-7 asthe current switch circuit of FIG. 3a. In addition, an inverter 10 isinserted between the input line and the input of the D-flipflop 2.Moreover, the overlapping control signals generated by the latch circuit3 and the inverters 4, 5 are each fed to the opposite transistors 7, 6as compared to FIG. 3a.

The current switch circuit of FIG. 3b works analogously to the currentswitch circuit of FIG. 3a, except that instead of the input signal IN,an inverted signal D is fed to the D-flipflop 2 and that the overlappingcontrol signals control the opposite transistors 7, 6 of thedifferential switch pair S as compared to FIG. 3a. As a result of theinversion of the input signal IN on the one hand and the changed accessof the overlapping control signals to the differential switch pair S onthe other hand, the differential switch pair S is basically controlledby signals of the same value as in FIG. 3a. And also in a current switchcircuit of FIG. 3b, the overlaps of the overlapping control signals areasymmetric. But the lengths of the overlaps for a switch from currentoutput OUT to current output XOUT and from current output XOUT tocurrent output OUT are exchanged compared to the lengths of the overlapsof the overlapping control signals in FIG. 3a.

Therefore, when employing a current switch circuit of FIG. 3a for halfof the current sources 1 of the MSB block and a current switch circuitof FIG. 3b for the other half of the current sources 1 of the MSB block,half of the state changes are complementary to the state changes of theother half. As a result, the distortion caused by the pulse relationerrors in the control signals spreads into the noise floor.

FIG. 5 shows a simulated spectrum of a 10-bit D/A converter of FIG. 1employing the control switch circuits of FIGS. 3a and 3 b for the 63current sources of the 6-bit MSB block, the sampling rate being 200 MHzand the signal frequency 20 MHz. The different control switch circuitswere distributed to the current sources as indicated in FIG. 4. Theoutput voltage V_(out) of the D/A converter is depicted over thefrequencies of the generated analog output.

When comparing the spectrum of FIG. 5 with the spectrum of FIG. 2 whichis based on the same 10-bit D/A converter except that a current switchcircuit of FIG. 3a was used for all current sources 1 of the 6-bit MSBblock, the improvement is obvious. The 2^(nd) harmonic component cannotbe distinguished anymore from the noise floor and the 3^(rd) harmoniccomponent which is now dominating limits the SFDR from 53 dB to 59 dB.

There is still some distortion left due to the uncompensatedbinary-weighted 4-bit LSB block.

The compensation is simple and does not increase the complexity of thecircuit and it can easily be transferred to higher resolutionconverters. For high resolution converters two or more unweightedcurrent source arrays can be used.

The compensation of asymmetries according to the invention was alsotested in a 13-bit D/A converter with a 7-bit MSB part to verify itssuitability in high-resolution D/A converters.

FIG. 6 shows the simulated spectrum of a 13-bit D/A converter withoutcompensation. The sample rate was 67 MHz and the signal frequency 5.5MHz. As can be seen in the figure, the dominating 2^(nd) harmoniccomponent is down 56 dB from the main signal.

FIG. 7 shows in contrast the simulated spectrum of a 13-bit D/Aconverter with a compensation according to the invention. The 3^(rd)harmonic component is now dominating with an SFDR of 67 dB, the 2^(nd)harmonic component being reduced to an SFDR of 80 dB. Accordingly, itwas possible to achieve a significant improvement with the compensationaccording to the invention also in a 13-bit D/A converter, even thoughthe used converter was not designed optimally for high-speedapplications and even though there was again no compensation for the 4current sources responsible for the 4-bit LSB part of the digitalsignals.

What is claimed is:
 1. A digital-to-analog converter comprising: a firstand a second current output (OUT, XOUT); at least two current sources(1), the currents of the current sources (1) being summed to form ananalog output signal; and a plurality of current switch circuit, whereineach switch circuit is assigned to one of the current sources (1) and isfor connecting its respective current source (1) to the first currentoutput (OUT) if the current source is selected according to a digitalinput signal and for connect the respective current source (1) to thesecond current output (XOUT) if the current source (1) is not selectedaccording to the digital input signal, wherein each current switchcircuit comprises: means (4, 5, 6, 7) for creating two overlappingcomplementary control signals out of a signal (IN) indicating whetherthe current source (1) is selected; wherein said plural switch circuitscomprise: a first group in which a connection of the respective currentsource (1) to the first current output (OUT) is controlled by a firstone of the overlapping control signals and a connection of the currentsource (1) to the second current output (XOUT) is controlled by a secondone of the overlapping control signals; and a second group in which theconnection of the respective current source (1) to the first currentoutput (OUT) is controlled by the second one of the overlapping controlsignals and the connection of the current source (1) to the secondcurrent output (XOUT) is controlled by the first one of the overlappingcontrol signals, wherein each of the current switch circuits of thesecond group further comprises: means (10) for inverting the signal(IN), thereby generating a signal (D), which is input to the means forcreating two overlapping complementary control signals.
 2. Thedigital-to-analog converter according to claim 1, wherein each currentswitch circuit further comprises: a clock input for inputting a clocksignal (CLX): and a means (2) for synchronizing the signal (IN or D)with the clock signal (CLX), before providing it to the means forcreating two overlapping complementary control signals.
 3. Thedigital-to-analog converter according to claim 2, wherein the means (2)for synchronizing the signal (IN or D) with the clock signal (CLK)outputs a synchronized signal (Q) and a complementary synchronizedsignal (QZ), and the two overlapping complementary control signals arecreated out of the synchronized signal (Q) and the complementarysynchronized signal (QZ).
 4. The digital-to-analog converter accordingto claim 2, wherein the means (2) for synchronizing the signal (IN or D)with the clock signal (CLK) comprises: a D-flipflop receiving at itssignal input the signal (IN or D) and at its clock input the clocksignal (CLK), wherein the clock signal (CLK) is equal for all currentswitch circuits of the digital-to-analog converter, and the D-flipflopsynchronizes said signal IN or D with the rising edge of the clocksignal (CLK).
 5. The digital-to-analog converter according to claim 1,wherein the means for creating two overlapping complementary controlsignals comprises: a latch circuit (3) with an inverter (4, 5) connectedto each of its outputs.
 6. The digital-to-analog converter according toclaim 1, wherein the current switch circuits comprising the first groupand the second group are assigned to unweighted current sources (1). 7.The digital-to-analog converter according to claim 1, wherein there areunweighted and weighted current sources, and only the current switchcircuits assigned to the unweighted current sources (1) comprise thefirst group and the second group.
 8. The digital-to-analog converteraccording to claim 1, wherein the number of current switch circuits inthe first group is basically the same as the number of current switchcircuits in the second group.
 9. The digital-to-analog converteraccording to claim 1, wherein the at least two current sources comprise:a double array of current sources (1), wherein current sources (1) ofone array are switched by the first group of current switch circuits andcurrent sources (1) of the other array are switched by the second groupof current switch circuits, each current source (1) of one of the arraysbeing switched simultaneously to one current source (1) of the otherarray.
 10. The digital-to-analog converter according to claim 1, whereinthe digital-to-analog converter is an integrated digital-to-analogconverter.
 11. A base station comprising the digital-to-analog converteraccording to claim
 1. 12. A radio relay transmitter comprising thedigital-to-analog converter according to claim
 1. 13. A method forreducing harmonic distortion in a digital-to-analog converter, whereinthe digital-to-analog converter comprises a first and a second currentoutput (OUT, XOUT) a plurality of current sources (1), the currents ofthe plural current sources (1) being summed up to form an analog outputsignal, and a plurality of current switch circuits, each current switchelement being assigned to one of the plural current sources (1) andbeing for connecting its respective current source (1) to the firstcurrent output (OUT) if the current source (1) is selected according toa digital input signal and for connecting the respective current source(1) to the second current output (XOUT) if the current source (1) is notselected according to the digital input signal, the method comprisingthe steps of: creating, for each current source (1) assigned to a firstgroup of the plural current sources, two overlapping control signalsbased on a signal (IN) indicating whether the respective current source(1) is selected, and using a first of said overlapping control signalsfor controlling a connection of the current source (1) to the firstcurrent output (OUT) and a second of said overlapping control signalsfor controlling a connection of the current source (1) to the secondcurrent output (XOUT); and creating, for each current source (1)assigned to a second group of the plural current sources two overlappingcontrol signals based on a signal (D) which is inverted compared to thesignal (IN) is selected, and using a first of said overlapping controlsignals for controlling a connection of the current source (1) to thesecond current output (XOUT) and a second of said control signals forcontrolling a connection of the current source (1) to the first currentoutput (OUT).